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for a function f(a,b,c) lets say and Em=(0,2,3,4,5,7)
E is used for summation**
the decoder would look like this right?
ignore the bottom circles, needed it to c/p
+ Show Spoiler +since Em is only 0,2,3,4,5 and 7... 1 and 6 would be tied to ground or we dont even touch it at all? i was wondering about this because the book has no examples if its like that. im unsure if we dont do shit to the 1/6 or tie it to ground.
another problem asks, consider the function f = w1`w3` + w2w3` + w1`w2 use the truth table to derive a circuit for f that uses a 2 to 1 multiplexer.
okay, since i asked a similar question like this on here before; i understand that(im breaking this in pieces):
w1'w3' ... w2 could either be a 0 or 1, basically we dont care.
w2w3' ... w1 could either be a 0 or 1, basically we dont care.
w1'w2 ... w3 could either be a 0 or 1, basically we dont care.
so i made my truth table looking like this:
since the function is in SOP, i used 1's
so far, am i correct? its an interesting dilemma since i have a hard time dealing with binary in my head. yeah its all 0's and 1's but i usually get myself trapped and lost in SOP/POS and gate truth tables. anyhow, i have that and then i would have to use a 2 to 1 multiplexer. i was wondering, do i need two 2to1's? because i would have 4 1's. thanks for reading whoever is familiar with this type of stuff.
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You might not want to listen to everyone who gives you advice. They might be spies for the Ban Raithed Initiative.
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lol half the people probably wont understand wtf this is either so they cant really "answer" my question(s). plus, this is just for my clarifications only. ive been trying to google different decoder/multiplexers for awhile(wont say hours) without any luck/results. i should of asked before spring break but everyone is gone until monday. >___>;
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you didn't articulate the first problem very well so I can't help you there.
the second problem is pretty straightforward. look at the three terms -
w1'w3' + w2'w3' + w1'w2
notice the second and third term have w2' and w2, respectively, and can be used to "control" the values of w1 and w3. so basically, to cover these two terms you can use w2' as your select bit for a 2-1 mux and w1' and w3' as your input bits. the first term can be covered with a very simple AND gate with shit inverted, then you can OR the AND gate and MUX units together.
That should be enough of a hint but let me know if you still can't figure it out.
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On March 21 2009 09:22 deathgod6 wrote:
You might not want to listen to everyone who gives you advice. They might be spies for the Ban Raithed Initiative.
shhhhhhh
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for the first problem, i suppose i didnt say "show how the function (which i stated in the OP) can be implemented using a 3-to-8 binary decoder and an OR gate. 3input, 8output and an OR gate. ive done that. so since the function is just that would i need to do anything to the other outputs(tie to ground).
as for the second problem, i made a typo. its suppose to be w1`w3` + w2w3` + w1`w2... the bar on top got me mixed up.
right, so since the function is now this, (the truth table is still correct, i just fucked up on the function typing it), which would be the select line? can there even be? there are no w1` to w1, i dont see any inverted.
since its like this, can i just choose an input and use that as a select line?
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Is this digital logic design? oh man i did not get this class at all lol
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Fuck, he's posting again? TT
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On March 21 2009 09:51 AoN.DimSum wrote:
Is this digital logic design? oh man i did not get this class at all lol
yeah, its digital logic design. the stuff gets rather messy and confusing mostly because im unsure which is the right answer and shit. and theres only 0's and 1's so theres not much you can do.
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thanks, its helpful although it doesnt explain what i wanted.
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i just took it last semester but i dont really remember much, srry 
oh btw did u draw a nand gate in the picture? I am not sure what you are looking for either.
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This should be what it looks like for question one if I am understanding it correctly, because the summation symbol just means F is one at (0,2,3,4,5,7) and you OR them because F is one at any of them.
Assuming your Truth table is correct, this is what the circuit looks like using one 2-1 mutiplex.
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On March 21 2009 10:26 Shivaz wrote:This should be what it looks like for question one if I am understanding it correctly, because the summation symbol just means F is one at (0,2,3,4,5,7) and you OR them because F is one at any of them. Assuming your Truth table is correct, this is what the circuit looks like using one 2-1 mutiplex.
so you split it like that....? holy fuck, i am in debt to you. and also, for #1, cant i use the alternate symbol of OR? when we did the decoders in class, we would always have a bubble at the end, i suppose in here we dont need to because of no inversion or can you explain why? thank you so much shivaz.
edit - for the multiplexer i think i understand the split, because w1 is either 1 or 2 so its used as a select line.
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The gate you used in your picture is in the form F = (A'xB' ) ' which is the same as F = A+B.
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